The folder ArtyA7-35_tools_2023.1_2024.2 contains HW and SW project files for Xilinx tools version 2023.1 and 2024.2.
The design was created on the Digilent Arty A7-35 (which is no longer in production), but can be upgraded to Arty A7-100.
The folder ArtyA7-100_tools_2025.1 contains HW and SW project files for Xilinx tools version 2025.1, where the board Digilent Arty A7-100 was used.
See the README files in these folders for details.
The main.cpp is the source file of the memory read speed benchmarking app, which is used in the SW projects. The source file is usable in both Vitis Classic and Vitis Unified (e.g., Vitis 2025.1).