@@ -19,11 +19,11 @@ namespace rpp_driver {
1919/* *
2020 * @brief Duplex Slave I2S controller class.
2121 * @details
22- * This class support the duplex communication of the I2S on the PIO port of the
23- * RP2040/2350 SoC MCU.
22+ * This class supports the duplex communication of the I2S on the PIO port of
23+ * the RP2040/2350 SoC MCU.
2424 *
2525 * The timing signal (BCLK and WS) of the I2S must be provided from the external
26- * device. This class support up to 192kHz Fs if the MCU system clock is higher
26+ * device. This class supports up to 192kHz Fs if the MCU system clock is higher
2727 * than 120MHz.
2828 *
2929 * The I2S pins can be mapped on the GPIO. This mapping is based on the
@@ -36,16 +36,24 @@ namespace rpp_driver {
3636 * -# BCLK
3737 * -# WS
3838 *
39+ * For example, let's assume SDTOUT is GPIO 15. Then, SDIN, BCLK and WS are
40+ * GPIO 16, 17 and 18 respectively.
41+ *
3942 * To start and stop the I2S transfer, call the Start() and the Stop() member
4043 * functions respectively.
4144 *
4245 * The audio sample in and out are through the GetFifoBlocking() and the
43- * PutFifoBlocking() member function , respectively. These are blocking function.
44- * That mean, program will wait until the data is ready, or FIFO has room for
45- * data.
46+ * PutFifoBlocking() member functions , respectively. These are blocking
47+ * function. That mean, program will wait until the data is ready, or FIFO has
48+ * room for data.
4649 *
4750 * This class assumes polling based data transfer instead of interrupt / DMA
4851 * based data transfer.
52+ *
53+ * Typically, program process the signal obtained from GetFifoBLock() and
54+ * output to PutFifoBLock(). To provide the high quality processing,
55+ * The first GetFifoBlocking() call should be as soon as possible, after
56+ * calling start() function.
4957 */
5058class I2sSlaveDuplex {
5159 private:
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