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Merge branch 'feature/8' into develop
2 parents 9987962 + fe3226e commit 69f1373

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Lines changed: 7 additions & 8 deletions

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CHANGELOG.md

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@@ -6,6 +6,8 @@ History of the project development
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### Changed
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- [Issue #4](https://github.com/suikan4github/rpp_driver/issues/4) Add gcov support for x86 build.
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- [Issue #5](https://github.com/suikan4github/rpp_driver/issues/5) Migrate action from hand-made to marketplace.
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- [Issue #8](https://github.com/suikan4github/rpp_driver/issues/8) Remove duplicated assertions in the adau1361lower.cpp.
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### Deprecated
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### Removed
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### Fixed

src/codec/adau1361lower.cpp

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@@ -86,10 +86,6 @@ void ::rpp_driver::Adau1361Lower::WaitPllLock(void) {
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// Configure PLL and start. Then, initiate the core and set the CODEC Fs.
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void ::rpp_driver::Adau1361Lower::ConfigurePll(unsigned int fs,
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unsigned int master_clock) {
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assert((fs == 24000 || fs == 32000 || fs == 48000 || fs == 96000 ||
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fs == 22050 || fs == 44100 || fs == 88200) &&
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"Bad Fs");
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if (fs == 24000 || fs == 32000 || fs == 48000 || fs == 96000) {
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// Configure the PLL. Target PLL out is 49.152MHz = 1024xfs
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// Regarding X, R, M, N, check ADAU1361 Datasheet register R1.
@@ -446,7 +442,7 @@ void ::rpp_driver::Adau1361Lower::ConfigurePll(unsigned int fs,
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}
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} else { // Fs must be checked at the top of this routine.
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assert(false && "Wrong parameter validation");
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assert(false && "Wrong Fs");
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}
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} // ConfigurePlll

test/test_adau1361lower.cpp

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@@ -1068,10 +1068,11 @@ TEST_F(Adau1361LowerDeathTest, ConfigurePll_wrong_fs) {
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// Test 27MHz master clock for Fs 48kHz series.
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{
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const unsigned int mclock = 8000000;
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const unsigned int fs = 192000;
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// check the assertion for bad mclock.
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const unsigned int fs = 192000; // FS 192kHz is not allowed.
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// check the assertion for bad mclock.
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#ifndef NDEBUG
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ASSERT_DEATH(codec_lower_->ConfigurePll(fs, mclock), "Bad Fs");
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ASSERT_DEATH(codec_lower_->ConfigurePll(fs, mclock),
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"Wrong Fs"); // Have to assert.
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#endif
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}
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} // ConfigurePll_wrong_fs

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