[AMDGPU] Analyze implicit reg operands when generating swaps (#192220)

Fix register usage analysis during swap generation by including implicit
register operands. Critical change was to replace MachineInstr uses/defs
with all_uses/all_defs.

---------

Signed-off-by: John Lu <John.Lu@amd.com>

Author: LU-JOHN

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

@@ -48,8 +48,8 @@ class SIShrinkInstructions {
   bool shrinkMadFma(MachineInstr &MI) const;
   ChangeKind shrinkScalarLogicOp(MachineInstr &MI) const;
   bool tryReplaceDeadSDST(MachineInstr &MI) const;
-  bool instAccessReg(iterator_range<MachineInstr::const_mop_iterator> &&R,
-                     Register Reg, unsigned SubReg) const;
+  bool instAccessReg(MachineInstr::filtered_const_mop_range &&R, Register Reg,
+                     unsigned SubReg) const;
   bool instReadsReg(const MachineInstr *MI, unsigned Reg,
                     unsigned SubReg) const;
   bool instModifiesReg(const MachineInstr *MI, unsigned Reg,
@@ -620,12 +620,9 @@ ChangeKind SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
 // This is the same as MachineInstr::readsRegister/modifiesRegister except
 // it takes subregs into account.
 bool SIShrinkInstructions::instAccessReg(
-    iterator_range<MachineInstr::const_mop_iterator> &&R, Register Reg,
+    MachineInstr::filtered_const_mop_range &&R, Register Reg,
     unsigned SubReg) const {
   for (const MachineOperand &MO : R) {
-    if (!MO.isReg())
-      continue;
-
     if (Reg.isPhysical() && MO.getReg().isPhysical()) {
       if (TRI->regsOverlap(Reg, MO.getReg()))
         return true;
@@ -641,12 +638,12 @@ bool SIShrinkInstructions::instAccessReg(
 
 bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, unsigned Reg,
                                         unsigned SubReg) const {
-  return instAccessReg(MI->uses(), Reg, SubReg);
+  return instAccessReg(MI->all_uses(), Reg, SubReg);
 }
 
 bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, unsigned Reg,
                                            unsigned SubReg) const {
-  return instAccessReg(MI->defs(), Reg, SubReg);
+  return instAccessReg(MI->all_defs(), Reg, SubReg);
 }
 
 TargetInstrInfo::RegSubRegPair

llvm/test/CodeGen/AMDGPU/v_swap_b32.mir

@@ -967,3 +967,22 @@ body:             |
     $vgpr1 = V_MOV_B32_e32 killed $vgpr3, implicit $exec, implicit $vgpr2, implicit-def $vgpr0_vgpr1, implicit killed $vgpr3
     S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
 ...
+
+# GCN-LABEL: negative_test_implicit_blocks_swap
+# GCN:      $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
+# GCN-NEXT: $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr0_sgpr1, 0, implicit-def $vgpr2
+# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
+# GCN-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+---
+name:            negative_test_implicit_blocks_swap
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
+    $vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
+    $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr0_sgpr1, 0, implicit-def $vgpr2
+    $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
+    $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
+    S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+...