Resolving boot issues

Author: Marvin Wewer

patch/u-boot/v2026.01/phy-allwinner-add-pcie-usb3-driver.patch

@@ -7,8 +7,8 @@ Signed-off-by: Marvin Wewer <mwewer37@proton.me>
 ---
  drivers/phy/allwinner/Kconfig                |   8 +
  drivers/phy/allwinner/Makefile               |   1 +
- drivers/phy/allwinner/phy-sun55i-pcie-usb3.c | 661 ++++++++++
- 3 files changed, 670 insertions(+)
+ drivers/phy/allwinner/phy-sun55i-pcie-usb3.c | 656 ++++++++++
+ 3 files changed, 665 insertions(+)
 
 diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
 index 111111111111..222222222222 100644
@@ -41,7 +41,7 @@ new file mode 100644
 index 000000000000..111111111111
 --- /dev/null
 +++ b/drivers/phy/allwinner/phy-sun55i-pcie-usb3.c
-@@ -0,0 +1,661 @@
+@@ -0,0 +1,656 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Allwinner PIPE USB3.0 PCIE Combo Phy driver
@@ -78,9 +78,6 @@ index 000000000000..111111111111
 +/* Sub-System Version Reset Register */
 +#define PCIE_USB3_SYS_VER		0x00
 +
-+/* PHY CLK Gating Control Register */
-+#define PCIE_REF_CLK_GATING 31
-+
 +/* CCMU Base Address */
 +#define SUNXI_CCMU_BASE                0x02001000
 +#define SUNXI_CCM_BASE                (SUNXI_CCMU_BASE)
@@ -595,9 +592,7 @@ index 000000000000..111111111111
 +    	reg_value |= (1 << PCIE_BRG_REG_RST);
 +    	writel(reg_value, PCIE_BGR_REG);
 +
-+    	reg_value = readl(0x2001a84);
-+    	reg_value |= (1 << PCIE_REF_CLK_GATING);
-+    	//reg_value = 0x81000001;
++    	reg_value = 0x81000001;
 +    	writel(reg_value, 0x2001a84);
 +
 +	pcie_usb3_sub_system_enable(combphy);